The present application relates to integrated circuits and, more particularly to a method and a structure that enable sufficient source/drain epitaxy growth to merge adjacent semiconductor fins in logic devices, while preventing epitaxy merging of adjacent semiconductor fins in embedded dynamic random access memory (eDRAM) devices.
As integrated circuits continue to scale downward in size, fin field effect transistors (FinFETs) are becoming increasingly attractive to be used in smaller nodes, e.g., the 22 nm node and beyond. Embedded dynamic random access memory (eDRAM) devices have been found to be a viable approach to boost chip performance. Integrated FinFET logic devices and eDRAM devices are becoming increasingly important for future scaled integrated circuits.
The current fabrication processes in the integration of logic and eDRAM FinFETs are complex because requirements for achieving high-performance logic devices are different from those for memory devices. For example, in these advanced circuits, the logic FinFETs require sufficient source/drain epitaxy growth to merge adjacent semiconductor fins so as to lower the source/drain resistance. However, such epitaxy growth process can cause undesired merging of adjacent semiconductor fins in eDRAM FinFETs. This may be problematic in that it can cause electrical shorts in eDRAM FinFETs. One way to circumvent the short problem in the eDRAM FinFETs is to reduce the extent of the source/drain epitaxy growth; however the insufficient source/drain epitaxy growth may cause high source/drain resistance and thus compromise the logic FinFET performance, particularly for those high performance logic FinFETs. As such, there remains a need to develop a method and a structure that would allow merging semiconductor fins in the logic devices, but not semiconductor fins in the memory devices, without adding additional steps and/or cost to manufacture.